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ds2232c version 1.4 ? future technology devices international ltd. 2005 page 1 of 54 FT2232C dual usb uart / fifo i.c. the FT2232C is the 3 rd generation of ftdis popular usb uart / fifo i.c. family. this device features two multi- purpose uart / fifo controllers which can be con?gured individually in several different modes. as well as a uart interface, fifo interface and bit-bang io modes of the 2 nd generation ft232bm and ft245bm devices, the FT2232C offers a variety of additional new modes of operation, including a multi-protocol synchronous serial engine interface which is designed speci?cally for synchronous serial protocols such as jtag and spi bus. hardware features ? single chip usb ? dual channel serial / parallel ports with a variety of con?gurations ? entire usb protocol handled on the chip...no usb- speci?c ?rmware programming required ? ft232bm-style uart interface option with full handshaking & modem interface signals ? uart interface supports 7 / 8 bit data, 1 / 2 stop bits, and odd / even / mark / space / no parity ? transfer data rate 300 to 1 mega baud (rs232) ? transfer data rate 300 to 3 mega baud (ttl and rs422 / rs485) ? auto transmit enable control for rs485 serial applications using txden pin ? ft245bm-style fifo interface option with bi- directional data bus and simple 4 wire handshake interface ? transfer data rate up to 1 megabyte / second ? enhanced bit-bang mode interface option ? new synchronous bit-bang mode interface option ? new multi-protocol synchronous serial engine (mpsse) interface option ? new mcu host bus emulation mode option ? new fast opto-isolated serial interface mode option ? interface mode and usb description strings con?gurable in external eeprom ? eeprom con?gurable on board via usb ? support for usb suspend and resume conditions via pwren#, and si / wu pins ? support for bus powered, self powered, and high- power bus powered usb con?gurations ? integrated power-on-reset circuit, with optional reset input and reset output pins ? 5v and 3.3v logic io interfacing with independent level conversion on each channel ? integrated 3.3v ldo regulator for usb io ? integrated 6mhz C 48mhz clock multiplier pll ? usb bulk or isochronous data transfer modes ? 4.35v to 5.25v single supply operating voltage range ? uhci / ohci / ehci host controller compatible ? usb 2.0 full speed (12 mbits / second) compatible ? compact 48-ld lqfp package virtual com port (vcp) drivers for ? windows 98 / 98 se / 2000 / me / xp ? linux 2.40 and greater ? windows ce ? mac os-8 and os-9** ? mac os-x d2xx (usb direct drivers + dll s/w interface) ? windows 98 / 98 se / 2000 / me / xp ? linux 2.4 and greater application areas ? usb ? dual port rs232 converters ? usb ? dual port rs422 / rs485 converters ? upgrading legacy peripheral designs to usb ? usb instrumentation ? usb jtag programming ? usb to spi bus interfaces ? usb industrial control ? field upgradable usb products ? galvanically isolated products with usb interface [ ** = in planning or under development ] 1.1 features summary 1.0 introduction
ds2232c version 1.4 ? future technology devices international ltd. 2005 page 2 of 54 FT2232C dual usb uart / fifo i.c. 1.2 general description the FT2232C is a usb interface which incorporates the functionallity of two of ftdi s second generation bm chips into a single device. a single downstream usb port is converted to two io channels which can each be individually con?gured as a ft232bm-style uart interface, or a ft245bm-style fifo interface, without the need to add a usb hub. there are also several new special modes which are either enabled in the external eeprom, or by using driver commands. these include synchronous bit-bang mode, a cpu-style fifo interface mode, a multi-protocol synchronous serial engine interface mode, mcu host bus emulation mode, and fast opto-isolated serial interface mode. in addition a new high drive level option means that the device uar t / fifo io pins will drive out at around three times the normal power level, meaning that the bus can be shared by several devices. classic bm-style asynchronous bit-bang mode is also supported, but has been enhanced to give the user access to the device s internal rd# and wr# strobes. ftdi provide a royalty free virtual com port (v.c.p) driver that makes the peripheral ports look like a standard com port to the pc. most existing software applications should be able interface with the v irtual com port simply by recon?guring them to use the new ports created by the driver. using the vcp drivers an application programmer would communicate with the device in exactly the same way as they would a regular pc com port - using the windows vcomm api calls or a com port library. the FT2232C driver also incorporates the functions de?ned for ftdis d2xx drivers, allowing applications programmers to interface software directly to the device using a windows dll. details of the driver and the programming interface can be found on ftdis website at www.ftdichip.co m .
ds2232c version 1.4 ? future technology devices international ltd. 2005 page 3 of 54 FT2232C dual usb uart / fifo i.c. ? two individually con?gurable io channels each of the FT2232Cs channels (a and b) can be individually con?gured as a ft232bm-style uart interface, or as a ft245bm-style fifo interface. in addition these channel can be con?gured in a number of special io modes. ? integrated power-on-reset (por) circuit the device incorporates an internal por function. a reset# pin is available to allow external logic to reset the device where required, however for most applications this pin can simply be hardwired to vcc. a rstout# pin is provided in order to allow the new por circuit to provide a stable reset to external mcu and other devices. ? integrated rcclk circuit used to ensure that the oscillator and clock multiplier pll frequency are stable prior to usb enumeration. ? integrated level converter on uart / fifo interface and control signals each channel of the FT2232C has its own independent vccio pin that can be supplied by between 3v to 5v. this allows each channels output voltage drive level to be individually con?gured. thus allowing, for example 3.3v logic to be interfaced to the device without the need for external level converter i.c.s. ? improved power management control for high- power usb bus powered devices the pwren# pin will become active when the device is enumerated by usb, and be deactivated when the device is in usb suspend. this can be used to directly drive a transistor or p-channel mosfet in applications where power switching of external circuitry is required. the bm pull down enable feature (con?gured in the external eeprom) is also retained. this will make the device gently pull down on the fifo / uart io lines when the power is shut off (pwren# is high). in this mode any residual voltage on external circuitry is bled to gnd when power is removed, thus ensuring that external circuitry controlled by pwren# resets reliably when power is restored. ? support for isochronous usb transfers whilst usb bulk transfer is usually the best choice for data transfer, the scheduling time of the data is not guaranteed. for applications where scheduling latency takes priority over data integrity such as transferring audio and low bandwidth video data, the FT2232C offers the option of usb isochronous transfer via con?guration of bit in the eeprom. ? send immediate / wake up signal pin on each channel there is a send immediate / wake up (si/wu) signal pins on each of the chips channels. these combine two functions on one pin. if usb is in suspend mode (and remote wakeup is enabled in the eeprom), strobing this pin low will cause the device to request a resume from suspend (wakeup) on the usb bus. normally, this can be used to wake up the host pc. during normal operation, if this pin is strobed low any data in the device rx buffer will be sent out over usb on the next bulk-in request from the drivers regardless of the packet size. this can be used to optimise usb transfer speed for some applications. ? low suspend current the suspend current of the FT2232C is typically under 100 a (excluding the 1.5k pull up resistor on usbdp) in usb suspend mode. this allows greater margin for peripherals to meet the usb suspend current limit of 500ua. the FT2232C incorporates all of the enhancements introduced for the second generation ft232bm and ft245bm chips. these are summarised as follows :- 2.0 features and enhancements
ds2232c version 1.4 ? future technology devices international ltd. 2005 page 4 of 54 FT2232C dual usb uart / fifo i.c. ? programmable receive buffer timeout the tx buffer timeout is programmable over usb in 1ms increments from 1ms to 255ms, thus allowing the device to be better optimised for protocols requiring faster response times from short data packets. ? relaxed vcc decoupling the improved level of vcc decoupling that was incorporated into bm devices has also been implemented in the FT2232C device. ? baud rate pre-scaler divisors the FT2232C (uart mode) baud rate pre-scaler supports division by (n+0), (n+0.125), (n+0.25), (n+0.375), (n+0.5), (n+0.625), (n+0.75) and (n+0.875) where n is an integer between 2 and 16,384 (2 14 ). ? extended eeprom support the FT2232C supports 93c46 (64 x 16 bit), 93c56 (128 x 16 bit), and 93c66 (256 x 16 bit) eeproms. the extra space is not used by the device, however it is available for use by other external mcu / logic whilst the FT2232C is being held in reset. there is now an adiitional 64 words of space available (128 bytes total) in the user area when a 93c56 or 93c66 is used. ? usb 2.0 (full speed option) an eeprom based option allows the FT2232C to return a usb 2.0 device descriptor as opposed to usb 1.1. note : the device would be a usb 2.0 full speed device (12mb/s) as opposed to a usb 2.0 high speed device (480mb/s).
ds2232c version 1.4 ? future technology devices international ltd. 2005 page 5 of 54 FT2232C dual usb uart / fifo i.c. ? enhanced asynchronous bit-bang interface the FT2232C supports ftdis bm chip bit bang mode. in bit bang mode, the eight fifo data lines can be switched between fifo interface mode and an 8-bit parallel io port. data packets can be sent to the device and they will be sequentially sent to the interface at a rate controlled by an internal timer (equivalent to the baud rate prescaler). with the FT2232C device this mode has been enhanced so that the internal rd# and wr# strobes are now brought out of the device which can be used to allow external logic to be clocked by accesses to the bit- bang io bus. ? synchronous bit-bang interface synchronous bit-bang mode differs from asynchronous bit-bang mode in that the device is only read when it is written to. thus making it easier for the controlling program to measure the response to an output stimulus as the data returned is synchronous to the output data. ? high output drive level capabillity the io interface pins can be made to drive out at three times the standard drive level thus allowing multiple devices, or devices that require a greater drive strength to be interfaced to the FT2232C. this option is con?gured in the external eeprom, ad can be set individually for each channel. ? multi-protocol synchronous serial engine interface (m.p.s.s.e.) the multi-protocol synchronous serial engine (mpsse) interface is a new option designed to interface ef?ciently with synchronous serial protocols such as jtag and spi bus. it is very ?exible in that it can be con?gured for different industry standards, or proprietary bus protocols. for instance, it is possible to connect one of the FT2232Cs channels to an sram con?gurable fpga as supplied by vendors such as altera and xilinx. the fpga device would normally be un-con?gured (i.e. have no de?ned function) at power-up. application software on the pc could use the mpsse to download con?guration data to the fpga over usb. this data would de?ne the hardwares function on power up. the other ft2232 channel would be available for other devices. this approach would allow a customer to create a generic usb peripheral, whos hardware function can be de?ned under control of the application software. the fpga based hardware could be easily upgraded or totally changed simply by changing the fpga con?guration data ?le. ( see ftdis morph- ic development module for a practicle example, www.morph-ic.co m ) ? mcu host bus emulation this new mode combines the a and b bus interface to make the FT2232C interface emulate a standard 8048 / 8051 style mcu bus. this allows peripheral devices for these mcu families to be directly attached to the FT2232C with io being performed over usb with the help of mpsse interface technology. ? fast opto-isolated serial interface a new proprietary ftdi protocol is designed to allow galvanically isolated devices to communicate sychronously with the FT2232C using just 4 signal wires (over two dual opto-isolators), and two power lines. the peripheral circuitry controls the data transfer rate in both directions, whilst maintaining full data integrity. maximum usb full speed data rates can be acheived. both a and b channels can communicate over the same 4 wire interface if desired. in addition to the bm chip features, the FT2232C incorporates the following new features and interface modes :-
ds2232c version 1.4 ? future technology devices international ltd. 2005 page 6 of 54 FT2232C dual usb uart / fifo i.c. x8 clock multiplier serial interface engine ( sie ) usb protocol engine dual port rx buffer 384 bytes dual port tx buffer 128 bytes 3.3 volt ldo regulator usb transceiver usb dpll 6mhz oscillator 48mhz 12mhz xtin xtout usbdp usbdm 3v3out vcc pwren# pwrctl eeprom interface eecs eesk eedata dual port rx buffer 384 bytes dual port tx buffer 128 bytes adbus0 adbus1 adbus2 adbus3 adbus4 adbus5 adbus6 adbus7 acbus0 acbus1 acbus2 acbus3 bdbus0 bdbus1 bdbus2 bdbus3 bdbus4 bdbus5 bdbus6 bdbus7 bcbus0 bcbus1 bcbus2 bcbus3 test gnd multi- purpose uart / fifo controller multi- purpose uart / fifo controller baud rate generator 48mhz baud rate generator 48mhz reset# reset generator rstout# 3v3out si/wua si/wub channel a channel b 3.0 simpli?ed block diagram 3.1 functional block descriptions ? 3.3v ldo regulator the 3.3v ldo regulator generates the 3.3 volt reference voltage for driving the usb transceiver cell output buffers. it requires an external decoupling capacitor to be attached to the 3v3out regulator output pin. it also provides 3.3v power to the rstout# pin. the main function of this block is to power the usb transceiver and the reset generator cells rather than to power external logic. however, external circuitry requiring 3.3v nominal at a current of not greater than 5ma could also draw its power from the 3v3out pin if required. ? usb transceiver the usb transceiver cell provides the usb 1.1 / usb 2.0 full-speed physical interface to the usb cable. the output drivers provide 3.3 volt level slew rate control signalling, whilst a differential receiver and two single ended receivers provide usb data in, seo and usb reset condition detection. ? usb dpll the usb dpll cell locks on to the incoming nrzi usb data and provides separate recovered clock and data signals to the sie block. figure 1 - FT2232C simpli?ed block diagram
ds2232c version 1.4 ? future technology devices international ltd. 2005 page 7 of 54 FT2232C dual usb uart / fifo i.c. ? 6mhz oscillator the 6mhz oscillator cell generates a 6mhz reference clock input to the x8 clock multiplier from an external 6mhz crystal or ceramic resonator. ? x8 clock multiplier the x8 clock multiplier takes the 6mhz input from the oscillator cell and generates a 48mhz reference clock for the usb dppl and the baud rate generator blocks. ? serial interface engine (sie) the serial interface engine (sie) block performs the parallel to serial and serial to parallel conversion of the usb data. in accordance to the usb 2.0 speci?cation, it performs bit stuf?ng / un- stuf?ng and crc5 / crc16 generation / checking on the usb data stream. ? usb protocol engine the usb protocol engine manages the data stream from the device usb control endpoint. it handles the low level usb protocol (chapter 9) requests generated by the usb host controller and the commands for controlling the functional parameters of the uart / fifo controller blocks. ? dual port tx buffers (128 bytes) data from the usb data out endpoint is stored in the dual port tx buffer and removed from the buffer to the transmit register under control of the uart fifo controller. ? dual port rx buffers (384 bytes) data from the uart / fifo controller receive register is stored in the dual port rx buffer prior to being removed by the sie on a usb request for data from the device data in endpoint. ? multi-purpose uart / fifo controllers the multi-purpose uart / fifo controllers handle the transfer of data between the dual port rx and tx buffers and the uart / fifo transmit and receive registers. when con?gured as a uart it performs asynchronous 7 / 8 bit parallel to serial and serial to parallel conversion of the data on the rs232 (rs422 and rs485) interface. control signals supported by uart mode include rts, cts, dsr , dtr, dcd and ri. there are also transmitter enable control signal pins (txden) provided to assist with interfacing to rs485 transceivers. rts/cts, dsr/dtr and xon/xoff handshaking options are also supported. handshaking, where required, is handled in hardware to ensure fast response times. the uarts also supports the rs232 break setting and detection conditions. ? baud rate generator the baud rate generator provides a x16 clock input to the uarts from the 48mhz reference clock and consists of a 14 bit prescaler and 3 register bits which provide ?ne tuning of the baud rate (used to divide by a number plus a fraction). this determines the baud rate of the uart which is programmable from 183 baud to 3 million baud. ? reset generator the reset generator cell provides a reliable power-on reset to the device internal circuitry on power up. an additional reset# input and rstout# output are provided to allow other devices to reset the FT2232C, or the FT2232C to reset other devices respectively. during reset, rstout# is driven low, otherwise it drives out at the 3.3v provided by the onboard regulator. rstout# can be used to control the 1.5k pull-up on usbdp directly where delayed usb enumeration is required. it can also be used to reset other devices. rstout# will stay high- impedance for approximately 5ms after vcc has risen above 3.5v and the device oscillator is running and reset# is high. reset# should be tied to vcc unless it is a requirement to reset the device from external logic or an external reset generator i.c.
ds2232c version 1.4 ? future technology devices international ltd. 2005 page 8 of 54 FT2232C dual usb uart / fifo i.c. ? eeprom interface when used without an external eeprom the FT2232C be con?gured as a usb to dual serial port device. adding an external 93c46 (93c56 or 93c66) eeprom allows each of the chips channels to be independently con?gured as a serial uart (232 mode), or a parallel fifo (245 mode). the external eeprom is used to enable the cpu-style fifo interface, and fast opto- isolated serial interface modes. the external eeprom can also be used to customise the usb vid, pid, serial number, product description strings and power descriptor value of the FT2232C for oem applications. other parameters controlled by the eeprom include remote wake up, isochronous transfer mode, soft pull down on power-off and usb 2.0 descriptor modes. the eeprom should be a 16 bit wide con?guration such as a microchip 93lc46b or equivalent capable of a 1mb/s clock rate at vcc = 4.35v to 5.25v. the eeprom is programmable- on board over usb using a utility program available from ftdis web site ( www.ftdichip.co m ). this allows a blank part to be soldered onto the pcb and programmed as part of the manufacturing and test process. if no eeprom is connected (or the eeprom is blank), the FT2232C will default to dual serial ports. the device use its built-in default vid, pid product description and power descriptor value. in this case, the device will not have a serial number as part of the usb descriptor.
ds2232c version 1.4 ? future technology devices international ltd. 2005 page 9 of 54 FT2232C dual usb uart / fifo i.c. figure 2 pin-out (lqfp-48 package ) figure 3 pin-out (schematic symbol ) 4.0 device pin-out eesk eedata vcc reset# rstout# 3v3out usbdp usbdm gnd gnd vcc xtout xtin agnd avcc test eecs 1 12 13 24 25 36 37 48 ftd i FT2232C xxyy gnd si/wua acbus3 acbus2 acbus1 vccioa acbus0 adbus7 adbus6 adbus5 adbus4 adbus3 adbus2 adbus1 adbus0 si/wub bcbus3 bcbus2 bcbus1 bcbus0 vcciob bdbus7 bdbus6 gnd bdbus5 bdbus4 pwren# bdbus3 bdbus2 bdbus1 bdbus0 24 23 22 21 20 19 17 16 26 41 6 8 7 5 43 44 4 48 1 47 2 4 6 3 4 2 1 4 4 5 1 8 9 3v3out usbdp usbdm rstout# xtin xtout reset# eecs eesk eedata test adbus0 adbus1 adbus2 adbus3 adbus4 adbus5 adbus6 adbus7 pwren# si/wub g n d g n d a g n d a v c c v c c v c c v c c i o a 3 4 2 5 g n d g n d 3 1 v c c i o b 15 13 12 11 acbus0 acbus1 acbus2 acbus3 40 39 38 37 36 35 33 32 bdbus0 bdbus1 bdbus2 bdbus3 bdbus4 bdbus5 bdbus6 bdbus7 30 29 28 27 bcbus0 bcbus1 bcbus2 bcbus3 10 si/wua
ds2232c version 1.4 ? future technology devices international ltd. 2005 page 10 of 54 FT2232C dual usb uart / fifo i.c. 5.0 pin de?nitions this section decribes the operation of the FT2232C pins. common pins are de? ned in the ?rst section, then the i/o pins are de?ned, by chip mode. more detailed descriptions of the operation of the i/o pins are provided in section 9. 5.1 common pins the operation of the following FT2232C pins stay the same, regardless of the chip mode :- usb interface group pin# signal type description 7 usbdp i/o usb data signal plus ( requires 1.5k pull-up to 3v3out or rstout# ) 8 usbdm i/o usb data signal minus eeprom interface group pin# signal type description 48 eecs i/o eeprom C chip select. tri-state during device reset. **note 1 1 eesk output clock signal to eeprom. tri-state during device reset, else drives out. **note 1 2 eedata i/o eeprom C data i/o connect directly to data-in of the eeprom and to data- out of the eeprom via a 2.2k resistor. also, pull data-out of the eeprom to vcc via a 10k resistor for correct operation. tri-state during device reset. **note 1 miscellaneous signal group pin# signal type description 4 reset# input can be used by an external device to reset the FT2232C. if not required, tie to vcc. **note 1 5 rstout# output output of the internal reset generator. drives low for 5.6 ms after vcc > 3.5v and the internal clock starts up, then clamps its output to the 3.3v output of the internal regulator. taking reset# low will also force rstout# to drive low. rstout# is not affected by a usb bus reset. 47 test input puts device into i.c. test mode C must be tied to gnd for normal operation. 41 pwren# output goes low after the device is con?gured via usb, then high during usb suspend. can be used to control power to external logic using a p-channel logic level mosfet switch. enable the interface pull-down option in eeprom when using the pwren# pin in this way. 43 xtin input input to 6mhz crystal oscillator cell. this pin can also be driven by an external 6mhz clock if required. note : switching threshold of this pin is vcc/2, so if driving from an external source, the source must be driving at 5v cmos level or a.c. coupled to centre around vcc/2. 44 xtout output output from 6mhz crystal oscillator cell. xtout stops oscillating during usb suspend, so take care if using this signal to clock external logic. **note 1 - during device reset, these pins are tri-state but pulled up to vcc via internal 200k resistors.
ds2232c version 1.4 ? future technology devices international ltd. 2005 page 11 of 54 FT2232C dual usb uart / fifo i.c. power and gnd group pin# signal type description 6 3v3out output 3.3 volt output from the integrated l.d.o. regulator this pin should be decoupled to gnd using a 33nf ceramic capacitor in close proximity to the device pin. its prime purpose is to provide the internal 3.3v supply to the usb transceiver cell and the rstout# pin. a small amount of current (<= 5ma) can be drawn from this pin to power external 3.3v logic if required. 3, 42 vcc pwr +4.35 volt to +5.25 volt vcc to the device core, ldo and non-uar t / fifo controller interface pins. 14 vccioa pwr +3.0 volt to +5.25 volt vcc to the uart / fifo a channel interface pins 10..13, 15..17 and 19..24. when interfacing with 3.3v external logic in a bus powered design connect vccio to a 3.3v supply generated from the usb bus. when interfacing with 3.3v external logic in a self powered design connect vccio to the 3.3v supply of the external logic. otherwise connect to vcc to drive out at 5v cmos level. 31 vcciob pwr +3.0 volt to +5.25 volt vcc to the uart / fifo b channel interface pins 26..30, 32..33 and 35..40. when interfacing with 3.3v external logic in a bus powered design connect vccio to a 3.3v supply generated from the usb bus. when interfacing with 3.3v external logic in a self powered design connect vccio to the 3.3v supply of the external logic. otherwise connect to vcc to drive out at 5v cmos level. 9,18, 25, 34 gnd pwr device - ground supply pins 46 avcc pwr device - analog power supply for the internal x8 clock multiplier. a low pass ?lter consisting of a 470 ohm series resistor and a 100 nf to gnd should be used on the supply to this pin. 45 agnd pwr device - analog ground supply for the internal x8 clock multiplier
ds2232c version 1.4 ? future technology devices international ltd. 2005 page 12 of 54 FT2232C dual usb uart / fifo i.c. 5.2 io pin de?nitions by chip mode the FT2232C will default to dual serial mode (232 uart mode on both channel a and b, if no external eeprom is used, or the external eeprom is blank. the de?nition of the following pins vary according to the chips mode :- channel a pin# generic pin name pin de?nitions by chip mode **note 2 232 uart mode 245 fifo mode enhanced asynchronous and synchronous bit-bang modes mpsse **note 4 mcu host bus emulation mode **note 5 fast opto- isolated serial mode 24 adbus0 txd d0 d0 tck/sk ad0 **note 3 23 adbus1 rxd d1 d1 tdi/d0 ad1 22 adbus2 rts# d2 d2 tdo/di ad2 21 adbus3 cts# d3 d3 tms/cs ad3 20 adbus4 dtr# d4 d4 gpiol0 ad4 19 adbus5 dsr# d5 d5 gpiol1 ad5 17 adbus6 dcd# d6 d6 gpiol2 ad6 16 adbus7 ri# d7 d7 gpiol3 ad7 15 acbus0 txden rxf# wr# **note 6 gpioh0 i/o0 13 acbus1 sleep# txe# rd# **note 6 gpioh1 i/o1 12 acbus2 rxled# rd# wr# **note 7 gpioh2 iordy 11 acbus3 txled# wr rd# **note 7 gpioh3 osc 10 si/wua si/wua si/wua si/wua **note 8 **note 8 **note 2 : 232 uart, 245 fifo, cpu fifo interface, and fast opto-isolated modes are enabled in the external eeprom. enhanced asynchronous and synchronous bit-bang modes, mpsse, and mcu host bus emulation modes are enabled using the driver command set bit mode. see section 5.2 for details. **note 3 : channel a can be con?gured in another io mode if channel b is in fast opto-isolated serial mode. if both channel a and channel b are in fast opto-isolated serial mode all of the io will be on channel b. **note 4 : mpsse is channel a only. **note 5 : mcu host bus emulation requires both channels. **note 6 : the bit-bang mode (synchronous and asynchronous) wr# and rd# strobes are on these pins when the main channel mode is 245 fifo, cpu fifo interface, or fast opto-isolated serial modes. **note 7 : the bit-bang mode (synchronous and asynchronous) wr# and rd# strobes are on these pins when the main channel mode is 232 uart mode. **note 8 : si/wu is not available in these modes .
ds2232c version 1.4 ? future technology devices international ltd. 2005 page 13 of 54 FT2232C dual usb uart / fifo i.c. channel b pin# generic pin name pin de?nitions by chip mode **note 2 232 uart mode 245 fifo mode enhanced asynchronous and synchronous bit-bang modes mpsse **note 4 mcu host bus emulation mode **note 5 fast opto- isolated serial mode 40 bdbus0 txd d0 d0 a8 fsdi 39 bdbus1 rxd d1 d1 a9 fsclk 38 bdbus2 rts# d2 d2 a10 fsdo 37 bdbus3 cts# d3 d3 a11 fscts 36 bdbus4 dtr# d4 d4 a12 **note 3 35 bdbus5 dsr# d5 d5 a13 33 bdbus6 dcd# d6 d6 a14 32 bdbus7 ri# d7 d7 a15 30 bcbus0 txden rxf# wr# **note 9 cs# 29 bcbus1 sleep# txe# rd# **note 9 ale 28 bcbus2 rxled# rd# wr# **note 7 rd# 27 bcbus3 txled# wr rd# **note 7 wr# 26 si/wub si/wub si/wub si/wub **note 8 **note 8 si/wub **note 2 : 232 uart, 245 fifo, cpu fifo interface, and fast opto-isolated modes are enabled in the external eeprom. enhanced asynchronous and synchronous bit-bang modes, mpsse, and mcu host bus emulation modes are enabled using the driver command set bit mode. see section 5.2 for details. **note 3 : channel a can be con?gured in another io mode if channel b is in fast opto-isolated serial mode. if both channel a and channel b are in fast opto-isolated serial mode all of the io will be on channel b. **note 4 : mpsse is channel a only. **note 5 : mcu host bus emulation requires both channels. **note 6 : the bit-bang mode (synchronous and asynchronous) wr# and rd# strobes are on these pins when the main channel mode is 245 fifo, cpu fifo interface, or fast opto-isolated serial modes. **note 7 : the bit-bang mode (synchronous and asynchronous) wr# and rd# strobes are on these pins when the main channel mode is 232 uart mode. **note 8 : si/wu is not available in these modes . **note 9 : the bit-bang mode (synchronous and asynchronous) wr# and rd# strobes are on these pins when the main channel mode is 245 fifo, cpu fifo interface. bit-bang mode is not available on channel b when fast opto- isolated serial mode is enabled.
ds2232c version 1.4 ? future technology devices international ltd. 2005 page 14 of 54 FT2232C dual usb uart / fifo i.c. 5.3 io mode command hex values enhanced asynchronous and synchronous bit-bang modes, mpsse, and mcu host bus emulation modes are enabled using the d2xx driver command ft_setbitmode. the hex values used with this command to enable these modes are as follows- mode value (hex) reset the io bit mode 0 asynchronous bit bang mode 1 mpsse 2 synchronous bit bang mode 4 mcu host bus emulation 8 fast opto-isolated serial mode 10 see application note an2232c-02 bit mode functions for the FT2232C for more details and examples. note that all other device modes can be enabled in the external eeprom, and do not require these values to be con?gured. in the case of fast opto-isolated serial mode sending a value of 10 will hold this device mode in reset, and sending a value of 0 will release this mode from reset.
ds2232c version 1.4 ? future technology devices international ltd. 2005 page 15 of 54 FT2232C dual usb uart / fifo i.c. 6.0 package outline the FT2232C is supplied in a 48 ld lqfp package as standard. this package has a 7mm x 7mm body (9mm x 9mm including leads) with leads on a 0.5mm pitch. the above drawing shows the lqfp-48 package C all dimensions are in millimetres. a lead free version of this package is also available, part number ft2232l. xxyy = date code ( xx = 2 digit week number, yy = 1 or 2 digit year number. figure 4 - 48 ld lqfp package dimensions pin# 1 0.25 1.60 max 12 o +/- 1 o 1.4 +/- 0.05 0.2 min 0.6 +/- 0.15 1.0 0.05 min 0.15 max 0.24 +/- 0.07 0.22 +/- 0.05 0.09 min 0.2 max 0.09 min 0.16 max 7 9 7 9 pin# 48 0.5 FT2232C ftdi xxyy 0.22+/- 0.05
ds2232c version 1.4 ? future technology devices international ltd. 2005 page 16 of 54 FT2232C dual usb uart / fifo i.c. 7.0 absolute maximum ratings these are the absolute maximum ratings for the FT2232C device i n accordance with the absolute maximum rating system (iec 60134). exceeding these may cause permanent damage to the device. ? storage temperature .............................. C65 o c to + 150 o c ? floor life (out of bag) at factory ambient (30 o c/60% relative humidity)........................192 hours **note 10 (level 3 compliant) ? ambient temperature (power applied).............................................. 0 o c to + 70 o c ? vcc supply voltage ..................................... -0.5v to +6.00v ? dc input voltage - inputs ................................. -0.5v to vcc + 0.5v ? dc input voltage - high impedance bidirectionals .............................. -0.5v to vcc + 0.5v ? dc output current C outputs ............................... 24ma ? dc output current C low impedance bidirectionals ................................ 24ma ? power dissipation (vcc = 5.25v) ................................ 500mw ? electrostatic discharge voltage (human body model) (i < 1a) ...................... +/- 3000v ? latch up current (vi = +/- 10v maximum, for 10 ms) ........................... +/-200ma **note 10 C if devices are stored out of the packaging beyond this time limit the devices should be baked before use. the devices should be ramped up to a temperature of 110 o c and baked for 8 to 10 hours.
ds2232c version 1.4 ? future technology devices international ltd. 2005 page 17 of 54 FT2232C dual usb uart / fifo i.c. 7.1 d.c. characteristics dc characteristics ( ambient temperature = 0 to 70 o c ) operating voltage and current parameter description min typ max units conditions vcc1 vcc operating supply voltage 4.35 5.0 5.25 v vcc2 vccio operating supply voltage 3.0 - 5.25 v icc1 operating supply current - 30 - ma normal operation icc2 operating supply current - 100 200 a usb suspend **note 11 **note 11 C supply current excludes the 200a nominal drawn by the external pull-up resistor on usbdp. io pin characteristics ( vccio = 5.0v, standard drive level ) **note 12 parameter description min typ max units conditions voh output voltage high 3.2 4.1 4.9 v i source = 2ma vol output voltage low 0.3 0.4 0.6 v i sink = 2ma vin input switching threshold 1.3 1.6 1.9 v vhys input switching hysteresis 50 55 60 mv io pin characteristics ( vccio = 3.0 - 3.6v, standard drive level ) **note 12 parameter description min typ max units conditions voh output voltage high 2.2 2.7 3.2 v i source = 1 ma vol output voltage low 0.3 0.4 0.5 v i sink = 2 ma vin input switching threshold 1.0 1.2 1.5 v vhys input switching hysteresis 20 25 30 mv io pin characteristics ( vccio = 5.0v, high drive level ) **note 12, **note 13 parameter description min typ max units conditions voh output voltage high 3.2 4.1 4.9 v i source = 6 ma vol output voltage low 0.3 0.4 0.6 v i sink = 6 ma vin input switching threshold 1.3 1.6 1.9 v vhys input switching hysteresis 50 55 60 mv io pin characteristics ( vccio = 3.0 - 3.6v, high drive level ) **note 12, **note 13 parameter description min typ max units conditions voh output voltage high 2.2 2.8 3.2 v i source = 3ma vol output voltage low 0.3 0.4 0.6 v i sink = 8 ma vin input switching threshold 1.0 1.2 1.5 v vhys input switching hysteresis 20 25 30 mv **note 12 : inputs have an internal 200k pull-up resistor to vccio, which can alternativly be programmed to pull down using a con?guration bit in the external eeprom. **note 12 : the high output drive level is con?gured in the external eeprom. each channel can be con?gured individually.
ds2232c version 1.4 ? future technology devices international ltd. 2005 page 18 of 54 FT2232C dual usb uart / fifo i.c. xtin / xtout pin characteristics parameter description min typ max units conditions voh output voltage high 4.0 - 5.0 v fosc = 6mhz vol output voltage low 0.1 - 1.0 v fosc = 6mhz vin input switching threshold 1.8 2.5 3.2 v reset#, test, eecs, eesk, eedata pin characteristics **note 14 parameter description min typ max units conditions voh output voltage high 3.2 4.1 4.9 v i source = 2ma vol output voltage low 0.3 0.4 0.6 v i sink = 2 ma vin input switching threshold 1.3 1.6 1.9 v vhys input switching hysteresis 50 55 60 mv **note 14 C eecs, eesk, eedata and reset# pins have an internal 200k pull-up resistor to vcc rstout# pin characteristics parameter description min typ max units conditions voh output voltage high 3.0 - 3.6 v i source = 2ma vol output voltage low 0.3 - 0.6 v i sink = 2ma usb io pin characteristics **note 15 parameter description min typ max units conditions uvoh io pins static output ( high) 2.8 - 3.6 v ri = 1.5k to 3v3out ( d+ ) ri = 15k to gnd ( d- ) uvol io pins static output ( low ) 0 - 0.3 v ri = 1.5k to 3v3out ( d+ ) ri = 15k to gnd ( d- ) uvse single ended rx threshold 0.8 - 2.0 v ucom differential common mode 0.8 - 2.5 v uvdif differential input sensitivity 0.2 - - v udrvz driver output impedance 29 - 44 ohm **note 15 C driver output impedance includes the external 27r series resistors on usbdp and usbdm pins.
ds2232c version 1.4 ? future technology devices international ltd. 2005 page 19 of 54 FT2232C dual usb uart / fifo i.c. 8.0 standard device con?guration examples 8.1 oscillator con?gurations figure 5 3-pin ceramic resonator con?guration figure 6 crystal or 2-pin ceramic resonator con?guration xtin xtout 44 FT2232C 3-pin resonator 6mhz 1m 43 xtin xtout 43 44 FT2232C 2 - pin resonator or crystal 6mhz 27pf 27pf figure 5 illustrates how to use the FT2232C with a 3-pin ceramic resonator . a suitable part would be a ceramic resonator from muratas ceralock range. (murata part number cstcr6m00g15), or equivalent. 3-pin ceramic resonators have the load capacitors built into the resonator so no external loading capacitors are required. this makes for an economical con?guration. the accuracy of this murata ceramic resonator is +/- 0.25% and it is speci?cally designed for usb full speed applications. a 1 megaohm loading resistor across xtin and xtout is recommended in order to guarantee this level of accuracy. other ceramic resonators with a lesser degree of accuracy (typically +/- 0.5%) are technically out-with the usb speci?cation, but it has been calculated that using such a device will work satisfactorily in practice with a FT2232C design. an example of such a device is muratas cstlsm00g53. figure 6 illustrates how to use the FT2232C with a 6mhz crystal or 2-pin ceramic resonator . in this case, these devices do not have in-built loading capacitors so these have to be added between xtin, xt out and gnd as shown. a value of 27pf is shown as the capacitor in the example C this will be good for many crystals and some resonators but do select the value based on the manufacturers recommendations wherever possible. if using a crystal, use a parallel cut type. if using a resonator, see the previous note on frequency accuracy. it is also possible to use a 6 mhz oscillator with the FT2232C. in this case the output of the oscillator would be connected to xtin, and xtout should be left unconnected. the oscillator must have a cmos output.
ds2232c version 1.4 ? future technology devices international ltd. 2005 page 20 of 54 FT2232C dual usb uart / fifo i.c. 8.2 eeprom con?guration figure 7 illustrates how to connect the FT2232C to the 93c46 (93c56 or 93c66) eeprom. eecs (pin 48) is directly connected to the chip select (cs) pin of the eeprom. eesk (pin 1) is directly connected to the clock (sk) pin of the eeprom. eedata (pin 2) is directly connected to the data in (din) pin of the eeprom. there is a potential condition whereby both the data output (dout) of the eeprom can drive out at the same time as the eedata pin of the FT2232C. to prevent potential data clash in this situation, the dout of the eeprom is connected to eedata of the FT2232C via a 2.2k resistor. following a power-on reset or a usb reset, the FT2232C will scan the eeprom to ?nd out (a) if an eeprom is attached to the device and (b) if the data in the device is valid. if both of these are the case, then the FT2232C will use the data in the eeprom, otherwise it will use its built-in default values and con?guration. the default port con?guration of the FT2232C puts both channel a and channel b into serial uart mode. when a valid command is issued to the eeprom from the FT2232C, the eeprom will acknowledge the command by pulling its dout pin low. in order to check for this condition, it is necessary to pull dout high using a 10k resistor. if the command acknowledge doesnt happen then eedata will be pulled high by the 10k resistor during this part of the cycle and the device will detect an invalid command or no eeprom present. 2.2k vcc eecs eedata 48 FT2232C eesk 1 2 2 cs sk din dout gnd nc nc vcc eeprom - 93c46 / 56 / 66 1 3 4 5 6 7 8 10k vcc figure 7 eeprom con?guration there are two varieties of 93c46/56/66 eeproms on the market C one is con?gured as being 16 bits wide, the other is con?gured as being 8 bits wide. these are available from many sources such as microchip, stmicro, issi etc. the FT2232C requires eeproms with a 16-bit wide con?guration such as the microchip 93lc46b device. the eeprom must be capable of reading data at a 1mb clock rate at a supply voltage of 4.35v to 5.25v . most available parts are capable of this. check the manufacturers data sheet to ?nd out how to connect pins 6 and 7 of the eeprom. some devices specify these as no-connect, others use them for selecting 8 / 16 bit mode or for test functions. some other parts have their pinout rotated by 90 o so please select the required part and its options carefully. it is possible to share the eeprom between the FT2232C and another external device such as an mcu. however , this can only be done when the FT2232C is in its reset condition as it tri-states its eeprom interface at that time. a typical con?guration would use four bits of an mcu io port. one bit would be used to hold the FT2232C reset (using reset#) on power-up, the other three would connect to the eecs, eesk and eeda ta pins of the FT2232C in order to read / write data to the eeprom at this time. once the mcu has read / written the eeprom, it would take reset# high to allow the FT2232C to con?gure itself and enumerate over usb. the external eeprom can be programmed over usb using utility software provided by ftdi. the external eeprom is used to enable 245 fifo, cpu-style fifo, and fast opto-isolated serial interface modes on each channel.
ds2232c version 1.4 ? future technology devices international ltd. 2005 page 21 of 54 FT2232C dual usb uart / fifo i.c. 8.3 usb bus powered and self powered con?guration figure 8 - usb bus powered con?guration figure 8 illustrates the FT2232C in a typical usb bus powered con? guration. a usb bus powered device gets its power from the usb bus. basic rules for usb bus power devices are as follows C a) on plug-in, the device must draw no more than 100ma b) on usb suspend the device must draw no more than 500a. c) a high power usb bus powered device (one that draws more than 100ma) should use the pwren# pin to keep the current below 100ma on plug-in and 500a on usb suspend. d) a device that consumes more than 100ma can not be plugged into a usb bus powered hub e) no device can draw more that 500ma from the usb bus. the power descriptor in the eeprom should be programmed to match the current draw required by the device. a ferrite bead is connected in series with usb power to prevent noise from the device and associated circuitry (emi) being radiated down the usb cable to the host. the value of the ferrite bead depends on the total current required by the circuit C a suitable range of ferrite beads is available from steward ( www.steward.co m ) for example steward part # mi0805k400r-00 also available from digikey, part # 240-1035-1. 0.1uf vcc 27r usb "b" connector 27r usb dm rstout# 8 FT2232C usb dp 7 5 v c c v c c v c c i o a 3 42 14 1 2 3 4 ferrite bead 1.5k 33nf 3v3out 6 470r a v c c 46 g n d g n d a g n d 18 25 34 10nf vcc reset# 4 decoupling capacitors 10uf vcc 0.1uf 0.1uf + 31 v c c i o a g n d g n d 9 45 test 47 eecs eesk eedata 10k 48 1 2 6mhz 27pf 27pf xtin 43 44 xtout 5
ds2232c version 1.4 ? future technology devices international ltd. 2005 page 22 of 54 FT2232C dual usb uart / fifo i.c. figure 9 - usb self powered con?guration figure 9 illustrates the FT2232C in a typical usb self powered con? guration. a usb self powered device gets its power from its own power supply and does not draw current from the usb bus. the basic rules for usb self power devices are as follows C a) a self-powered device should not force current down the usb bus when the usb host or hub controller is powered down. b) a self powered device can take as much current as it likes during normal operation and usb suspend as it has its own power supply. c) a self powered device can be used with any usb host and both bus and self powered usb hubs. the usb power descriptor option in the eeprom should be programmed to a value of zero (self powered). to meet requirement a) the 1.5k pull-up resistor on usbdp is connected to rstout# as per the bus-power circuit. however, the usb bus power is used to control the reset# pin of the FT2232C device. when the usb host or hub is powered up rstout# will pull the 1.5k resistor on usbdp to 3.3v, thus identifying the device as a full speed device to usb. when the usb host or hub power is off, reset# will go low and the device will be held in reset. as reset# is low, rstout# will also be low, so no current will be forced down usbdp via the 1.5k pull-up resistor when the host or hub is powered down. failure to do this may cause some usb host or hub controllers to power up erratically. note : when the FT2232C is in reset, the i/o interface pins all go tri-state. these pins have internal 200k pull-up resistors to vccio, so they will gently pull high unless driven by some external logic. vcc 27r usb "b" connector 27r usb dm rstout# 8 FT2232C usb dp 7 5 v c c v c c v c c i o a 3 42 14 1 2 3 4 1.5k 33nf 3v3out 6 470r a v c c 46 0.1uf g n d g n d a g n d 45 25 34 reset# 4 10k 4.7k decoupling capacitors 10uf vcc 0.1uf 0.1uf + v c c i o b 31 test 9 18 47 g n d g n d
ds2232c version 1.4 ? future technology devices international ltd. 2005 page 23 of 54 FT2232C dual usb uart / fifo i.c. 8.4 interfacing to 3.3v logic figure 10 - bus powered circuit with 3.3v logic drive and io supply voltage figure 10 shows how to con?gure the FT2232C to interface with a 3.3v logic devices. in this example, a discrete 3.3v regulator is used to supply the 3.3v logic from the usb supply. vccioa and vcciob are connected to the output of the 3.3v regulator, which in turn will cause the device interface io pins on both channels to drive out at 3.3v level. it is also possible to have one io interface channel driving out at 5v level, and the other at 3.3v level. in this case one of the vccio pins would be connected to 5v, and the other connected to 3.3v. for usb bus powered circuits some considerations have to be taken into account when selecting the regulator C a) the regulator must be capable of sustaining its output voltage with an input voltage of 4.35 volts. a low drop out (ldo) regulator must be selected. b) the quiescent current of the regulator must be low in order to meet the usb suspend total current requirement of <= 500a during usb suspend. an example of a regulator family that meets these requirements is the microchip (t elcom) tc55 series. these devices can supply up to 250ma current and have a quiescent current of under 1a. ferrite bead 470r 0.1uf vcc 27r usb "b" connector 27r usb dm 8 FT2232C usb dp 7 v c c v c c v c c i o a 3 42 14 1 2 3 4 33nf 3v3out 6 a v c c 46 10nf 0.1uf in out gnd 3.3v ldo regulator 3.3v power to external logic v c c i o b 31 rstout# 1.5k decoupling capacitors 10uf vcc 0.1uf 0.1uf + 5 vcc reset# test 4 47 g n d g n d a g n d 18 25 34 g n d g n d 9 45 vcc3v3 vcc3v3 vcc3v3 si/wua si/wub 10 26
ds2232c version 1.4 ? future technology devices international ltd. 2005 page 24 of 54 FT2232C dual usb uart / fifo i.c. figure 11 is an example of a FT2232C usb self powered design with 3.3v interface. in this case the vccioa and vcciob pins are supplied by an external 3.3v supply in order to make both of the device s io channels drive out at 3.3v logic level, thus allowing them to be connected to a 3.3v mcu or other external logic. it is also possible to have one io interface channel driving out at 5v level, and the other at 3.3v level. in this case one of the vccio pins would be connected to 5v, and the other connected to 3.3v. in some cases, where only a small amount of current is required (< 5ma) , it may be possible to use the in-built regulator of the FT2232C to supply the 3.3v without any other components being required. in this case, connect vccioa or vcciob to the 3v3out pin of the FT2232C. note : it should be emphasised that the 3.3v supply for vccio in a bus powered design with a 3.3v logic interface should come from an ldo which is supplied by the usb bus, or from the 3v3out pin of the ft232bm, and not from any other source. please also note that if the si/wu pins are not being used they should be pulled up to the same supply as their respective vccio pin. figure 11 - self powered circuit with 3.3v logic drive and io supply voltage vcc5v 27r usb "b" connector 27r usb dm rstout# 8 usb dp 7 5 v c c i o a 31 1 2 3 4 1.5k 33nf 3v3out 6 0.1uf g n d g n d a g n d 9 18 45 reset# 4 10k 4.7k decoupling capacitors 10uf 0.1uf 0.1uf + vcc3v3 v c c v c c 3 42 470r a v c c 46 v c c i o b 14 si/wua si/wub 10 26 vcc3v3 vcc3v3 test vcc5v g n d g n d 25 34 FT2232C 47
ds2232c version 1.4 ? future technology devices international ltd. 2005 page 25 of 54 FT2232C dual usb uart / fifo i.c. a usb self powered design uses its own power supplies, and does not draw any of its power from the usb bus. in such cases, no special care need be taken to meet the usb suspend current (0.5 ma) as the device does not get its power from the usb port. as with bus powered 3.3v interface designs, in some cases, where only a small amount of current is required (<5ma), it may be possible to use the in-built regulator of the FT2232C to supply the 3.3v without any other components being required. in this case, connect vccioa or vcciob to the 3v3out pin of the FT2232C. note that if the si/wu pins are not being used they should be pulled up to the same supply as their respective vccio pin.
ds2232c version 1.4 ? future technology devices international ltd. 2005 page 26 of 54 FT2232C dual usb uart / fifo i.c. 8.5 power switching figure 12 - bus powered circuit with power control usb bus powered circuits need to be able to power down in usb suspend mode in order to meet the <= 500a total suspend current requirement (including external logic). some external logic can power itself down into a low current state by monitoring the pwren# pin. for external logic that cannot power itself down in that way , the FT2232C provides a simple but effective way of turning off power to external circuitry during usb suspend. figure 12 shows how to use a discrete p-channel logic level mosfet to control the power to external logic circuits. a suitable device would be an international recti?er ( www.irf.co m ) irlml6402, or equivalent. it is recommended that a soft start circuit consisting of a 1k series resistor and a 0.1 f capacitor are used to limit the current surge when the mosfet turns on. without the soft start circuit there is a danger that the transient power surge of the mosfet turning on will reset the FT2232C, or the usb host / hub controller . the values used here allow attached circuitry to power up with a slew rate of ~12.5 v per millisecond, in other words the output voltage will transition from gnd to 5v in approximately 400 microseconds. usb "b" connector ferrite bead 470r 0.1uf vcc 27r 27r usb dm 8 FT2232C usb dp 7 v c c v c c v c c i o b 3 42 31 1 2 3 4 33nf 3v3out 6 a v c c 46 10nf pwren# 41 0.1uf switched 5v power to external logic p-channel power mosfet s g d 0.1uf 1k soft start circuit v c c i o a 14 rstout# 1.5k reset# vcc decoupling capacitors 10uf vcc 0.1uf 0.1uf + 4 5
ds2232c version 1.4 ? future technology devices international ltd. 2005 page 27 of 54 FT2232C dual usb uart / fifo i.c. figure 13 is a FT2232C design example which effectively combines the circuits shown in figures 13 and 14 to give a usb bus powered design with power switching and 3.3v logic drive level on both channels. once again a p-channel power mosfet and soft start circuit are used to control the power to external logic devices. a 3.3v ldo regulator which is supplied by the usb bus is used to provide the 3.3v supply for the vccio pins, as well as the external logic. if the si/wu pins are not being used they should be pulled up to 3.3v . alternatively, a dedicated power switch i.c. with inbuilt soft-start can be used instead of a mosfet. a suitable power switch i.c. for such an application would be a micrel ( www.micrel.co m ) mic2025-2bm or equivalent. please note the following points in connection with power controlled designs C a) the logic to be controlled must have its own reset circuitry so that it will automatically reset itself when power is re- applied on coming out of suspend. b) set the pull-down on suspend option in the FT2232Cs eeprom. c) for usb high-power bus powered device (one that consumes greater than 100 ma, and up to 500 ma of current from the usb bus), the power consumption of the device should be set in the max power ? eld in the eeprom. a high-power bus powered device must use this descriptor in the eeprom to inform the system of its power requirements. d) for 3.3v power controlled circuits the vccio pins must not be powered down with the external circuitry . either connect the power switch between the output of the 3.3v regulator and the external 3.3v logic, or if appropriate power the vccio pin from the 3v3out pin of the FT2232C. figure 13 - bus powered circuit with power control and 3.3v logic drive / io supply voltage usb "b" connector ferrite bead 470r 0.1uf vcc5v 27r 27r usb dm 8 ft2232 usb dp 7 v c c v c c v c c i o b 3 42 31 1 2 3 4 33nf 3v3out 6 a v c c 46 10nf pwren# 41 0.1uf switched 3.3v power to external logic p-channel power mosfet s g d 0.1uf 1k soft start circuit v c c i o a 14 rstout# 1.5k reset# vcc5v decoupling capacitors 10uf vcc5v 0.1uf 0.1uf + 4 5 3.3v ldo regulator in out gnd 0.1uf si/wub si/wua vcc3v3 vcc3v3 vcc3v3 26 10
ds2232c version 1.4 ? future technology devices international ltd. 2005 page 28 of 54 FT2232C dual usb uart / fifo i.c. 9.0 signal descriptions by io mode and interface channel con?gurations 9.1 232 uart interface mode signal descriptions and interface con? gurations when either channel a or channel b are in 232 uart mode the io signal lines are con?gured as follows:- pin# signal type description channel a channel b 24 40 txd output transmit asynchronous data output 23 39 rxd input receive asynchronous data input **note 16 22 38 rts# output request to send control output / handshake signal 21 37 cts# input clear to send control input / handshake signal **note 16 20 36 dtr# output data terminal ready control output / handshake signal 19 35 dsr# input data set ready control input / handshake signal **note 16 17 33 dcd# input data carrier detect control input **note 16 16 32 ri# input ring indicator control input. when the remote wake up option is enabled in the eeprom, taking ri# low can be used to resume the pc usb host controller from suspend. **note 16 15 30 txden output enable transmit data for rs485 13 29 sleep# output goes low during usb suspend mode. typically used to power- down an external ttl to rs232 level converter i.c. in usb to rs232 converter designs. 12 28 rxled# o.c. led drive - pulses low when transmitting data via usb. 11 27 txled# o.c led drive - pulses low when receiving data via usb. 10 26 si/wu input the send immediate / wakeup signal combines two functions on a single pin. if usb is in suspend mode (pwren# = 1) and remote wakeup is enabled in the eeprom , strobing this pin low will cause the device to request a resume on the usb bus. normally, this can be used to wake up the host pc. during normal operation (pwren# = 0), if this pin is strobed low any data in the device tx buffer will be sent out over usb on the next bulk-in request from the drivers regardless of the pending packet size. this can be used to optimise usb transfer speed for some applications. tie this pin to vccio if not used. **note 16 : these pins are pulled to up vccio via internal 200k resistors during reset and usb suspend mode. these can be programmed to gently pull low during usb suspend ( pwren# = 1 ) by setting this option in the eeprom.
ds2232c version 1.4 ? future technology devices international ltd. 2005 page 29 of 54 FT2232C dual usb uart / fifo i.c. figure 14 illustrates how to connect the FT2232C, when both channels a and b are con?gured as 232-style uart interfaces, to two ttl C rs232 level converter i.c.s to make a usb <=> dual port rs232 converter using the popular 213 series of ttl to rs232 level converters. these devices have 4 transmitters and 5 receivers in a 28- ld ssop package and feature an in-built voltage converter to convert the 5v (nominal) vcc to the +/- 9 volts required by rs232. an important feature of these devices is the shdn# pin which can power down the device to a low quiescent current during usb suspend mode. the device used in the example above is a sipex sp213ehca which is capable of rs232 communication at up to 500k baud. if a lower baud rate is acceptable, then several pin compatible alternatives are available such as the sipex sp213eca , the maxim max213cai and the analog devices adm213e, which are all good for communication at up to 115,200 baud. if a higher baud rate is desired, use a maxim max3245cai part which is capable of rs232 communication at rates of up to 1m baud. the max3245 is not pin compatible with the 213 series devices, also its shdn pin is active high, so connect it to pwren# instead of sleep#. dual rs232 level converters such as the maxim max3187 may also be a suitable alternative. figure 14 - usb <=> dual port rs232 converter con?guration 12 14 2 7 8 4 6 1 9 vcc sp213ehca t1in t1out t2out t3out t4out r1in t2in t3in t4in r2in r3in r4in r5in vcc r1out r2out r3out r4out r5out shdn# 25 7 22 20 8 6 5 26 19 21 11 2 23 1 9 3 4 27 18 28 vcc c1+ c1- c2+ c2- v c c v- v+ 15 16 10 11 3 13 17 g n d vcc 0.1uf 0.1uf 0.1uf 0.1uf 0.1uf 5 FT2232C sleep# (acbus1) txd (adbus0) rxd (adbus1) rts# (adbus2) rts# (adbus3) dtr# (adbus4) dsr# (adbus5) dcd# (adbus6) ri# (adbus7) 13 txden (acbus0) 24 23 22 21 20 19 17 16 15 db9-m rs232 channel a txd_a rxd_a rts_a dtr_a cts_a dsr_a dcd_a ri_a gnd 29 40 39 38 37 36 35 33 32 30 pwren# 41 12 14 2 7 8 4 6 1 9 vcc sp213ehca t1in t1out t2out t3out t4out r1in t2in t3in t4in r2in r3in r4in r5in vcc r1out r2out r3out r4out r5out shdn# 25 7 22 20 8 6 5 26 19 21 11 2 23 1 9 3 4 27 18 28 vcc c1+ c1- c2+ c2- v c c v- v+ 15 16 10 11 3 13 17 g n d vcc 0.1uf 0.1uf 0.1uf 5 txd_b rxd_b rts_b dtr_b cts_b dsr_b dcd_b ri_b gnd db9-m rs232 channel b sleep# (bcbus1) txd (bdbus0) rxd (bdbus1) rts# (bdbus2) cts# (bdbus3) dtr# (bdbus4) dsr# (bdbus5) dcd# (bdbus6) ri# (bdbus7) txden (bcbus0)
ds2232c version 1.4 ? future technology devices international ltd. 2005 page 30 of 54 FT2232C dual usb uart / fifo i.c. figure 15 illustrates how to connect the uart interfaces of the FT2232C to two ttl C rs422 level converter i.c.s to make a usb to dual port rs422 converter. there are many such level converter devices available C this example uses two sipex sp491 devices which have enables on both their transmitters and receivers. because the transmitter enables are active high, they are connected to the sleep# pins. the receiver enables are active low and are both connected to the pwren# pin. this ensures that both the transmitters and receivers are enabled when the device is active, and disabled when the device is in usb suspend mode. if the design is usb bus powered, it may be necessary to use a p-channel logic level mosfet (controlled by pwren#) in the vcc line of the sp491 devices to ensure that the usb standby current of 500a is met. the sp491 is good for sending and receiving data at a rate of up to 5m baud C in this case the maximum rate is limited to 3m baud by the FT2232C. figure 15 - usb <=> rs422 converter con?guration FT2232C txdm_a rxdp_a rtsp_a ctsp_a gnd vcc 5 4 12 9 3 11 2 10 14 7 6 d r sp491 5 4 12 9 3 11 2 10 14 7 6 d r sp491 vcc 120r 120r txdp_a rxdm_a rtsm_a ctsm_a sleep# (acbus1) txd (adbus0) rxd (adbus1) rts# (adbus2) cts# (adbus3) dtr# (adbus4) dsr# (adbus5) dcd# (adbus6) ri# (adbus7) 13 txden (acbus0) 24 23 22 21 20 19 17 16 15 pwren# 41 sleep# (bcbus1) txd (bdbus0) rxd (bdbus1) rts# (bdbus2) cts# (bdbus3) dtr# (bdbus4) dsr# (bdbus5) dcd# (bdbus6) ri# (bdbus7) 29 txden (bcbus0) 40 39 38 37 36 35 33 32 30 txdm_b rxdp_b rtsp_b ctsp_b gnd vcc 5 4 12 9 3 11 2 10 14 7 6 d r sp491 5 4 12 9 3 11 2 10 14 7 6 d r sp491 vcc 120r 120r txdp_b rxdm_b rtsm_b ctsm_b db9-m rs422 channel b db9-m rs422 channel a
ds2232c version 1.4 ? future technology devices international ltd. 2005 page 31 of 54 FT2232C dual usb uart / fifo i.c. figure 16 - usb <=> rs485 converter con?guration figure 16 illustrates how to connect the uart interfaces of the FT2232C to two ttl C rs485 level converter i.c.s to make a usb to dual port rs485 converter. this example uses two sipex sp491 devices but there are similar parts available from maxim and analog devices amongst others. the sp491 is a rs485 device in a compact 8 pin sop package. it has separate enables on both the transmitter and receiver . with rs485, the transmitter is only enabled when a character is being transmitted from the uart. the txden pins on the FT2232C are provided for exactly that purpose, and so the transmitter enables are wired to the txdens. the receiver enable is active low, so it is wired to the pwren# pin to disable the receiver when in usb suspend mode. rs485 is a multi-drop network C i.e. many devices can communicate with each other over a single two wire cable connection. the rs485 cable requires to be terminated at each end of the cable. links are provided to allow the cable to be terminated if the device is physically positioned at either end of the cable. in this example the data transmitted by the FT2232C is also received by the device that is transmitting. this is a common feature of rs485 and requires the application software to remove the transmitted data from the received data stream. with the FT2232C it is possible to do this entirely in hardware C simply modify the schematic so that rxd of the FT2232C is the logical or of the sp481 receiver output with txden using an hc32 or similar logic gate. db9-m rs485 channel a dm_a gnd 120r dpa vcc 4 3 6 2 1 7 8 5 d r sp481 link FT2232C sleep# (acbus1) txd (adbus0) rxd (adbus1) rts# (adbus2) cts# (adbus3) dtr# (adbus4) dsr# (adbus5) dcd# (adbus6) ri# (adbus7) 13 txden (acbus0) 24 23 22 21 20 19 17 16 15 pwren# 41 sleep# (bcbus1) txd (bdbus0) rxd (bdbus1) rts# (bdbus2) cts# (bdbus3) dtr# (bdbus4) dsr# (bdbus5) dcd# (bdbus6) ri# (bdbus7) 29 txden (bcbus0) 40 39 38 37 36 35 33 32 30 db9-m rs485 channel b dm_b gnd 120r dp_b vcc 4 3 6 2 1 7 8 5 d r sp481 link
ds2232c version 1.4 ? future technology devices international ltd. 2005 page 32 of 54 FT2232C dual usb uart / fifo i.c. 9.2 232 uart mode led interface figure 17 dual led con?guration figure 18 single led con?guration FT2232C txled# rxled# vccio 220r led FT2232C txled# rxled# vccio 220r 220r tx rx when con?gured in uart mode the FT2232C has two io pins on each channel dedicated to controlling led status indicators, one for transmitted data the other for received data. when data is being transmitted / received the respective pins drive from tri-state to low in order to provide indication on the led s of data transfer. a digital one-shot timer is used so that even a small percentage of data transfer is visible to the end user . figure 17 shows a con?guration using two individual leds C one for transmitted data the other for received data. in figure 18, the transmit and receive led indicators are wire-ored together to give a single led indicator which indicates any transmit or receive data activity. another possibility (not shown here) is to use a 3 pin common anode tri-color led based on the circuit in figure 18 to have a single led that can display activity in a variety of colors depending on the ratio of transmit activity compared to receive activity. note that the leds are connected to the same supply as vccio.
ds2232c version 1.4 ? future technology devices international ltd. 2005 page 33 of 54 FT2232C dual usb uart / fifo i.c. 9.3 245 fifo interface mode signal descriptions and con?guration when either channel a or channel b are in 245 fifo mode the io signal lines are con?gured as follows. fifo data bus group **note 17 pin# signal type description channel a channel b 24 40 d0 i/o fifo data bus bit 0 23 39 d1 i/o fifo data bus bit 1 22 38 d2 i/o fifo data bus bit 2 21 37 d3 i/o fifo data bus bit 3 20 36 d4 i/o fifo data bus bit 4 19 35 d5 i/o fifo data bus bit 5 17 33 d6 i/o fifo data bus bit 6 16 32 d7 i/o fifo data bus bit 7 fifo control interface group pin# signal type description channel a channel b 15 30 rxf# output when high, do not read data from the fifo. when low, there is data available in the fifo which can be read by strobing rd# low then high again ** note 18 13 29 txe# output when high, do not write data into the fifo. when low, data can be written into the fifo by strobing wr high then low. ** note 18 12 28 rd# input enables current fifo data byte on d0..d7 when low. fetches the next fifo data byte (if available) from the receive fifo buffer when rd# goes from low to high. ** note 17 11 27 wr input writes the data byte on the d0..d7 into the transmit fifo buffer when wr goes from high to low. ** note 17 10 26 si/wu input the send immediate / wakeup signal combines two functions on a single pin. if usb is in suspend mode (pwren# = 1) and remote wakeup is enabled in the eeprom , strobing this pin low will cause the device to request a resume on the usb bus. normally, this can be used to wake up the host pc. during normal operation (pwren# = 0), if this pin is strobed low any data in the device tx buffer will be sent out over usb on the next bulk-in request from the drivers regardless of the pending packet size. this can be used to optimise usb transfer speed for some applications. tie this pin to vccio if not used. **note 17 : i n input mode, these pins are pulled to vccio via internal 200k resistors. these can be programmed to gently pull low during usb suspend ( pwren# = 1 ) by setting this option in the eeprom. **note 18 : during device reset, these pins are tri-state but pulled up to vccio via internal 200k resistors.
ds2232c version 1.4 ? future technology devices international ltd. 2005 page 34 of 54 FT2232C dual usb uart / fifo i.c. 245 fifo mode timing diagrams figure 19 - fifo read cycle time description min max unit t1 rd# active pulse width 50 ns t2 rd# to rd pre-charge time 50 + t6 ns t3 rd# active to valid data ** note 19 20 50 ns t4 valid data hold time from rd# inactive ** note 19 0 ns t5 rd# inactive to rxf# 0 25 ns t6 rxf# inactive after rd# cycle 80 ns ** note 19 : load 30 pf at standard drive level. these times will also vary if the high output drive level is enabled. figure 20 - fifo write cycle time description min max unit t7 wr active pulse width 50 ns t8 wr to wr pre-charge time 50 ns t9 data setup time before wr inactive 20 ns t10 data hold time from wr inactive 0 ns t11 wr inactive to txe# 5 25 ns t12 txe inactive after wr cycle 80 ns rxf# rd# d[7...0] t3 t1 t5 t6 t2 t4 valid data valid data d[7...0] wr txe# t7 t12 t11 t8 t9 t10
ds2232c version 1.4 ? future technology devices international ltd. 2005 page 35 of 54 FT2232C dual usb uart / fifo i.c. figure 21 - microprocessor interface example figure 21 illustrates a typical interface between one of the channels of the FT2232C, con? gured in 245-style fifo interface mode, and a microcontroller (mcu). either channel a or b, or both can be con?gured in this mode. this examples uses two io ports of the mcu, one port (8 bits) to transfer data to one of the and the other port (4 / 5 bits) to monitor the txe# and rxf# status bits and generate the rd# and wr strobes to the FT2232C as required. optionally, si / wu can be connected to another io pin if either of the functions of this pin are required. if the si / wu function is not required, tie this pin to vccio. if the mcu is handling power management functions, then pwren# should also be connected to an io pin of the mcu. the 8 data bits on io port 1 can be shared with other peripherals when the mcu is not accessing the FT2232C. d0 d1 d2 d3 d4 d5 d6 d7 rd# si / wu rxf# wr txe# FT2232C io10 io11 io12 io13 io14 io15 io16 io17 io20 io24 io23 io21 io22 microcontroller io port 1 io port 2 ( optional ) pwren# io25 ( optional ) 41 channel a or b
ds2232c version 1.4 ? future technology devices international ltd. 2005 page 36 of 54 FT2232C dual usb uart / fifo i.c. 9.5 enhanced asynchronous and synchronous bit-bang modes - signal description and interface con?guration bit-bang mode is a special FT2232C device mode that changes the 8 io lines on either (or both) channels into an 8 bit bi-directional data bus. the are two types of bit bang mode for the FT2232C - enhanced asynchronous bit-bang mode, which is virtually the same as ftdi bm chip-style bit-bang mode, with the addition of read and w rite strobes; and synchronous bit-bang mode, where data is only read from the device when the device is written to. bit-bang mode is enabled by driver command. when either channel a or channel b (or both) have enhanced asynchronous bit-bang mode, or synchronous bit-bang mode enabled the io signal lines are con? gured as follows :- bit-bang data bus group **note 24 pin# signal type description channel a channel b 24 40 d0 i or o bit-bang data bus bit 0 23 39 d1 i or o bit-bang data bus bit 1 22 38 d2 i or o bit-bang data bus bit 2 21 37 d3 i or o bit-bang data bus bit 3 20 36 d4 i or o bit-bang data bus bit 4 19 35 d5 i or o bit-bang data bus bit 5 17 33 d6 i or o bit-bang data bus bit 6 16 32 d7 i or o bit-bang data bus bit 7 pin# signal type description channel a channel b 15 30 wr# output **note 25 13 29 rd# output **note 25 12 28 wr# output **note 26 11 27 rd# output **note 26 10 26 si/wu input the send immediate / wakeup signal combines two functions on a single pin. if usb is in suspend mode (pwren# = 1) and remote wakeup is enabled in the eeprom , strobing this pin low will cause the device to request a resume on the usb bus. normally, this can be used to wake up the host pc. during normal operation (pwren# = 0), if this pin is strobed low any data in the device tx buffer will be sent out over usb on the next bulk-in request from the drivers regardless of the pending packet size. this can be used to optimise usb transfer speed for some applications. tie this pin to vccio if not used. **note 24 : in input mode, these pins are pulled to vccio via internal 200k resistors. these can be programmed to gently pull low during usb suspend ( pwren# = 1 ) by setting this option in the eeprom. bit-bang control interface group
ds2232c version 1.4 ? future technology devices international ltd. 2005 page 37 of 54 FT2232C dual usb uart / fifo i.c. **note 25 : the bit-bang mode (synchronous and asynchronous) wr# and rd# strobes are on these pins when the main channel mode is 245 fifo, cpu fifo interface, or fast opto-isolated serial mode. bit-bang mode is not available on channel b when fast opto-isolated serial mode is enabled. **note 26 : the bit-bang mode (synchronous and asynchronous) wr# and rd# strobes are on these pins when the main channel mode is set to 232 uart mode. enhanced asynchronous bit-bang mode enhanced asynchronous bit-bang mode is the same as bm-style bit-bang mode, except that the internal rd# and wr# strobes are now brought out of the device to allow external logic to be clocked by accesses to the bit-bang io bus. on either or both channels any data written to the device in the normal manner will be self clocked onto the data pins (those which have been con?gured as outputs). each pin can be independently set as an input or an output. the rate that the data is clocked out at is controlled by the baud rate generator . for the data to change there has to be new data written, and the baud rate clock has to tick. if no new data is written to the channel, the pins will hold the last value written. to allow time for the data to be setup and held around the wr# strobe, the baud rate should be less than 1 megabaud. see the application note an232b-01, ft232bm/ft245bm bit bang mode for more details and a sample application. enabling asynchronous bit-bang mode is enabled using set bit bang mode driver command. a hex value of 1 will enable it, and a hex value of 0 will reset the device. see application note an2232c-02, bit mode functions for the FT2232C for more details and examples of this.
ds2232c version 1.4 ? future technology devices international ltd. 2005 page 38 of 54 FT2232C dual usb uart / fifo i.c. synchronous bit-bang mode with synchronous bit-bang mode data will only be sent out by the FT2232C if there is space in the device for data to be read from the pins. this synchronous bit-bang mode will read the data bus pins ?rst, before it sends out the byte that has just been transmitted. it is therefore 1 byte behind the output, and so to read the inputs for the byte that you have just sent, another byte must be sent. for example :- (1) pins start at 0xff send 0x55,0xaa pins go to 0x55 and then to 0xaa data read = 0xff,0x55 (2) pins start at 0xff send 0x55,0xaa,0xaa (repeat the last byte sent) pins go to 0x55 and then to 0xaa data read = 0xff,0x55,0xaa
ds2232c version 1.4 ? future technology devices international ltd. 2005 page 39 of 54 FT2232C dual usb uart / fifo i.c. enabling synchronous bit-bang mode is enabled using set bit bang mode driver command. a hex value of 4 will enable it, and a hex value of 0 will reset the device. see application note an2232c-02, bit mode functions for the FT2232C for more details and examples. figure 25 - synchronous bit bang mode signal timing clk time d7..0 t1 t2 t3 t4 t5 t6 wr# rd# current data new data time description t1 current pin state is read t2 rd# is set inactive t3 rd# is set active again, and any pins that are output will change to the new data. t4 clock state for data setup t5 wr# goes active t6 wr# goes inactive the internal rd# and wr# strobes are brought out of the device to allow external logic to be clocked by accesses to the bit-bang io bus.
ds2232c version 1.4 ? future technology devices international ltd. 2005 page 40 of 54 FT2232C dual usb uart / fifo i.c. 9.6 multi-protocol synchronous serial engine (mpsse) mode signal descriptions and interface con?gurations mpsse mode is designed to allow the FT2232C to interface ef?ciently with synchronous serial protocols such as jtag and spi bus. it can also be used to program sram based fpgas over usb. the mpsse interface is designed to be ?exible so that it can be con?gured to allow any synchronous serial protocol (industry standard or proprietary) to be interfaced to the FT2232C. mpsse is available on channel a only. mpsse is fully con?gurable, and is programmed by sending commands down the data pipe. these can be sent individually, or more ef?ciently in packets. mpsse is capable of a maximum sustained data rate of 5.6 mega bits / s . when channel a is con?gured in mpsse mode the io signal lines are con?gured as follows :- pin# (channel a only) signal type description 24 tck/sk output clock signal output 23 tdi/d0 output serial data out 22 tdo/di input serial data in **note 27 21 tms/cs output select signal out 20 gpiol0 i/o general pupose input / output **note 27 19 gpiol1 i/o general pupose input / output **note 27 17 gpiol2 i/o general pupose input / output **note 27 16 gpiol3 i/o general pupose input / output **note 27 15 gpioh0 i/o general pupose input / output **note 27 13 gpioh1 i/o general pupose input / output **note 27 12 gpioh2 i/o general pupose input / output **note 27 11 gpioh3 i/o general pupose input / output **note 27 **note 27 : in input mode, these pins are pulled to vccio via internal 200k resistors. these can be programmed to gently pull low during usb suspend ( pwren# = 1 ) by setting this option in the eeprom. enabling mpsse mode is enabled using set bit bang mode driver command. a hex value of 2 will enable it, and a hex value of 0 will reset the device. see application note an2232c-02, bit mode functions for the FT2232C for more details and examples. the mpsse command set is fully described in application note an2232c-01 - command processor for mpsse and mcu host bus emulation modes .
ds2232c version 1.4 ? future technology devices international ltd. 2005 page 41 of 54 FT2232C dual usb uart / fifo i.c. 9.7 mcu host bus emulation mode signal descriptions and interface con? guration mcu host bus emulation mode uses both of the FT2232Cs a and b channel interfaces to make the chip emulate a standard 8048 / 8051 mcu host bus. this allows peripheral devices for these mcu families to be directly connected to usb via the FT2232C. the lower 8 bits (ad7 to ad0) is a multiplexed address / data bus. a8 to a15 provide upper (extended) addresses. there are 4 basic operations :- 1) read (does not change a15 to a8) 2) read extended (changes a15 to a8) 3) write (does not change a15 to a8) 4) write extended (changes a15 to a8) enabling mcu host bus emulation mode is enabled using set bit bang mode driver command. a hex value of 8 will enable it, and a hex value of 0 will reset the device. see application note an2232c-02, bit mode functions for the FT2232C for more details and examples. the mcu host bus emulation mode command set is fully described in application note an2232c-01 - command processor for mpsse and mcu host bus emulation modes .
ds2232c version 1.4 ? future technology devices international ltd. 2005 page 42 of 54 FT2232C dual usb uart / fifo i.c. when mcu host bus emulation mode is enabled the io signal lines on both channels work together and the pins are con?gured as follows :- pin# signal type description 24 ad0 i/o address / data bus bit 0 **note 28 23 ad1 i/o address / data bus bit 1 **note 28 22 ad2 i/o address / data bus bit 2 **note 28 21 ad3 i/o address / data bus bit 3 **note 28 20 ad4 i/o address / data bus bit 4 **note 28 19 ad5 i/o address / data bus bit 5 **note 28 17 ad6 i/o address / data bus bit 6 **note 28 16 ad7 i/o address / data bus bit 7 **note 28 15 i/o0 i/o mpsse mode instructions to set / clear or read the high byte of data can be used with this pin. **note 28, **note 29 13 i/o1 i/o mpsse mode instructions to set / clear or read the high byte of data can be used with this pin. in addition this pin has instructions which will make the controller wait until it is high, or wait until it is low. this can be used to connect to an irq pin of a peripheral chip. the FT2232C will wait for the interrupt, and then read the device, and pass the answer back to the host pc. i/o1 must be held in input mode if this option is used. **note 28, **note 29 12 iordy input extends the time taken to perform a read or write operation if pulled low. pull up to vcc if not being used. 11 osc output shows the clock signal that the circuit is using. 40 a8 output extended address bus bit 8 39 a9 output extended address bus bit 9 38 a10 output extended address bus bit 10 37 a11 output extended address bus bit 12 36 a12 output extended address bus bit 13 35 a13 output extended address bus bit 14 33 a14 output extended address bus bit 15 32 a15 output extended address bus bit 16 30 cs# output negative pulse to select device during read or write. 29 ale output positive pulse to latch the address. 28 rd# output negative read output. 27 wr# output negative write output. (data is setup before wr# goes low, and is held after wr# goes high) **note 28 : in input mode, these pins are pulled to vccio via internal 200k resistors. these can be programmed to gently pull low during usb suspend ( pwren# = 1 ) by setting this option in the eeprom. **note 29 : these instrucions are fully described in the application note an2232c-01 - command processor for mpsse and mcu host bus emulation modes .
ds2232c version 1.4 ? future technology devices international ltd. 2005 page 43 of 54 FT2232C dual usb uart / fifo i.c. figure 29 - mcu host bus emulation mode signal timing - write cycle osc a15..a8 ad7..0 ale cs# wr# high address low address data t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 iordy time description t1 high address byte is placed on the bus if the extended write is used. t2 low address byte is put out. t3 1 clock period for address is set up. t4 ale goes high to enable latch. this will extend to 2 clocks wide if iordy is low. t5 ale goes low to latch address and cs# is set active low. t6 data driven onto the bus. t7 1 clock period for data setup. t8 wr# is driven active low. this will extend to 6 clocks wide if iordy is low. t9 wr# is driven inactive high. t10 cs# is driven inactive, 1/2 a clock period after wr# goes inactive t11 data is held until this point, and may now change
ds2232c version 1.4 ? future technology devices international ltd. 2005 page 44 of 54 FT2232C dual usb uart / fifo i.c. figure 30 - mcu host bus emulation mode signal timing - read cycle osc a15..a8 ad7..0 ale cs# rd# high address low address t1 t2 t3 t4 t5 t6 t7 t8 t9 iordy hi-z time description t1 high address byte is placed on the bus if the extended read is used - otherwise t1 will not occur . t2 low address byte is put out. t3 1 clock period for address set up. t4 ale goes high to enable address latch. this will extend to 2 clocks wide if iordy is low. t5 ale goes low to latch address, and cs# is set active low. this will extend to 3 clocks if iordy is sampled low. cs# will always drop 1 clock after ale has gone high no matter the state of iordy. t6 data is set as input (hi-z), and rd# is driven active low. t7 1 clock period for data setup. this will extend to 5 clocks wide if iordy# is sampled low. t8 rd# is driven inactive high. t9 cs# is driven inactive 1/2 a clock period after rd# goes inactive, and the data bus is set back to output. figure 31 - mcu host bus emulation mode signal timing - clock (osc) signal osc t high t low t period time description minimum typical value maximum unit t period clock period 41.6 83.3 125.0 ns t high clock signal high time 20.8 41.6 62.5 ns t low clock signal low time 20.8 41.6 62.5 ns
ds2232c version 1.4 ? future technology devices international ltd. 2005 page 45 of 54 FT2232C dual usb uart / fifo i.c. figure 32 - mcu host bus emulation example - usb <=> can bus interface i/o0 (acbus0) i/o1 (acbus1) iordy# (acbus2) FT2232C sja1000 canbus controller address / data bus ad[0...7] (adbus[0...7]) wr# rd# ad[0...7] 15 13 12 cs# (bcbus0) wr# (bcbus3) ale (bcbus1) rd# (bcbus2) 30 29 28 27 cs# ale/as vcc mode vcc int# rx tx canbus transeiver can bus figure 32 shows an example where the FT2232C is used to interface a philips sja1000 can bus controller to a pc over usb. in this example iordy is not used and so is pulled up to vcc. i/o1 is used to monitor the interrupt output (int) of the sja1000. the mode pin on the sja1000 is pulled high to select intel mode. see the semiconductors section of the philips website ( www.philips.co m ) for more details on the sja1000, and suitable can bus transceiver devices.
ds2232c version 1.4 ? future technology devices international ltd. 2005 page 46 of 54 FT2232C dual usb uart / fifo i.c. 9.8 fast opto-isolated serial interface mode signal description and con? guration fast opto-isolated serial interface mode provides a method of communicating with an external device over usb using 4 wires that can have opto-isolators in their path, thus providing galvanic isolation between systems. if either channel a or channel b are enabled in fast opto-isolated serial mode then the pins on channel b are switched to the fast serial interface con?guration. the i/o interface for fast serial mode is always on channel b, even if both channels are being used in this mode. an address bit is used to determine the source or destination channel of the data. it therefore makes sense to always use at least channel b or both for fast serial mode, but not a own its own. when either channel b or both channel a and b are con?gured in fast opto-isolated serial interface mode following io signal lines are con?gured as follows :- pin# signal type description 40 fsdi input fast serial data input **note 30 39 fsclk input clock input to FT2232C chip to clock data in or out. the external device has to provide a clock signal or nothing will change on the interface pins. this gives the external device full control over the interface. it is designed to be half duplex so that data is only transferred in one direction at a time. **note 30 38 fsdo output fast serial data output. driven low to indicate that the chip is ready to send data. 37 fscts output clear to send control signal output 26 si/wu input the send immediate / wakeup signal combines two functions on a single pin. if usb is in suspend mode (pwren# = 1) and remote wakeup is enabled in the eeprom , strobing this pin low will cause the device to request a resume on the usb bus. normally, this can be used to wake up the host pc. during normal operation (pwren# = 0), if this pin is strobed low any data in the device tx buffer will be sent out over usb on the next bulk-in request from the drivers regardless of the pending packet size. this can be used to optimise usb transfer speed for some applications. tie this pin to vccio if not used. **note 30 : pulled up to vccio via internal 200k resistors. these pins can be programmed to gently pull low during usb suspend ( pwren# = 1 ) by setting this option in the eeprom. fast opto-isolated serial interface mode is enabled in the external eeprom.
ds2232c version 1.4 ? future technology devices international ltd. 2005 page 47 of 54 FT2232C dual usb uart / fifo i.c. time description min max unit t1 fsdo / fscts hold time 5 - ns t2 fsdo / fscts setup time 5 - ns t3 fsdi hold time 5 - ns t4 fsdi setup time 10 - ns t5 fsclk low 10 - ns t6 fsclk high 10 - ns t7 fsclk period 20 - ns outgoing fast serial data to send fast serial data out of the chip, the external device must clock. if the chip has data ready to send, it will drive fsdo low to indicate the start bit. it will not do this if it is currently receiving data from the external device. figure 34 - fast opto-isolated serial data format - data output from the FT2232C notes :- (i) start bit is always 0. (ii) data is sent lsb ?rst. (iii) the source bit (srce) indicates which channel the data has come from. a 0 means that it has come from chan - nel a, a 1 means that it has come from channel b. (iv) if the target device is unable to accept the data when it detects the start bit, it should stop the fsclk until it can accept the data. figure 33 - fast opto-isolated serial signal timing diagram fsdo / fscts fsclk fsdi t1 t2 t3 t4 t5 t6 t7 fsclk fsdo 0 d0 d1 d2 d3 d4 d5 d6 d7 srce start bit data bits - lsb first source bit
ds2232c version 1.4 ? future technology devices international ltd. 2005 page 48 of 54 FT2232C dual usb uart / fifo i.c. incoming fast serial data the external device is allowed to send data into the chip if fscts is high. on receipt of a zero start bit on fsdi, the chip will drop fscts on the next positive clock edge. the data from bits 0 to 7 is then clocked in (lsb ?rst). the next bit determines where the data will be written to. it can go to either channel a or to channel b. a 0 will send it to channel a, providing channel a is enabled for fast serial mode, otherwise it will go to channel b. a 1 will send it to channel b, providing channel b is enabled for fast serial mode, otherwise it will go to channel a. ( either channel a, or channel b, or both must be enabled as fast serial mode or the circuit is disabled). figure 35 - fast opto-isolated serial data format - data input to the FT2232C notes :- (i) start bit is always 0. (ii) data is sent lsb ?rst. (iii) the destination bit (dest) indicates which channel the data should go to. a 0 means that it should go to channel a, a 1 means that it should go to channel b. (iv) the target device should check cts is high before it sends data. cts goes low after data bit 0 (d0) and stays low until the chip can accept more data. contention there is a possibility that contention may occur, where the interface goes from being completely idle to both sending and receiving at the same clock instance. in this case the chip backs of f, and allows the data from the external device to be received. data format the data format for either direction is :- 1) zero start bit 2) data bit 0 3) data bit 1 4) data bit 2 5) data bit 3 6) data bit 4 7) data bit 5 8) data bit 6 9) data bit 7 10) source/destination (0 indicates channel a; 1 indicates channel b) fsclk fsdi 0 d0 d1 d2 d3 d4 d5 d6 d7 dest start bit data bits - lsb first destination bit fscts
ds2232c version 1.4 ? future technology devices international ltd. 2005 page 49 of 54 FT2232C dual usb uart / fifo i.c. reset / enable fast serial mode is enabled by setting the appropriate bits in the external eeprom. the fast serial mode can be held in reset by setting a bit value of 10 using the set bit bang mode command. while this bit is set the device is held reset - data can be sent to the device, but it will not be sent out by the device until the device is enabled again. this is done by sending a bit value of 0 using the set bit mode command. see application note an2232c-02, bit mode functions for the FT2232C for more details and examples. figure 36 - fast opto-isolated serial interface example FT2232C 40 39 38 37 fsdi (bdbus0) fsclk (bdbus1) fsdo (bdbus2) fscts (bdbus0) vcc5v hcpl-2430 vcce hcpl-2430 1k 1k 1k 1k 470r 470r 470r 470r vcce cable di clk do cts vcc5v 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 in the example shown in ?gure 12 two agilent hcpl-2430 (see the semiconductor section at www.agilent.co m ) high speed opto-couplers are used to optically isolate an external device which interfaced to usb using the FT2232C. in this example vcc5v is the supply for the FT2232C (bus or self powered), and vcce is the supply to the external device. care must be taken with the voltage used to power the photoleds. it should be the same supply that the i/os are driving to, or the leds may be permanently on. limiting resistors should be ?tted in the lines that drive the diodes. the outputs of the opto-couplers are open-collector and so need a pullup resistor . testing fast serial mode has been tested using an scenix (ubicom), sx28 microcontroller (see www.ubicom.co m ) which was con?gured in loopback mode. this was done both with, and without hp hcpl-2430 opto-isolators in place. the isolators add a considerable delay to the turnaround time seen by the micro. this was close to 100 ns with the high speed hcpl-2430 device. this is the combined delay of the clock signal from the microcontroller going through an opto-coupler to the chip, and the data from the FT2232C chip going through the other opto-coupler back to the microcontroller.
ds2232c version 1.4 ? future technology devices international ltd. 2005 page 50 of 54 FT2232C dual usb uart / fifo i.c. 10.0 document revision history ds2232c version 1.0 C initial document created january 2004. ds2232c version 1.1 C updated february 2004. ? grammar corrections ? section 4.0 device pin out figure 2 corrected. ? section 5.1 test pin number corrected. ? section 5.1 vccioa and vcciob pin descriptions updated. ? section 9.1 figure 14 sp214ehca pin numbers corrected. ? section 12.0 company contact information updated. ds2232c version 1.2 C updated april 2004. ? section 1.1 linux now supported. ? section 2.0 extended eeprom support corrected. ? section 2.0 synchronous bit-bang mode description clari?ed. ? section 4.0 figure 3 pin 46 avcc name corrected. ? section 5.2 note 2 modi?ed. ? section 5.3 io mode command hex values added. ? section 8.1 additional murata part number added. ? section 8.3 test pin number added to ?gure 8. ? section 8.3 test pin number and missing gnd added to ?gure 9. ? section 8.4 si/wu pin numbers added to ?gure 10. ? section 8.4 test pin number added to ?gure 11. ? section 9.3 fifo write cycle timings ameded. figure 19 amended. ? section 9.5 synchronous bit-bang mode description ameded. ? sections 9.5, 9.6, 9.7, and 9.8 enabling io bit mode clari?ed. ? section 12.0 email addresses updated. ds2232c version 1.3 C updated july 2004. ? section 1.1 windows ce now supported. ? section 5.2 io pin de?nition table. pins 32, 33, 35 - 40. mcu host bus emulation signal names corrected. ds2232c version 1.4 C updated july 2004. ? section 1.1 d2xx for windows ce and linux now supported. ? section 5.2 cpu fifo interface mode removed. ? section 6.0 date code format corrected. ? section 6.0 lead free version (ft2232l) now available. ? section 9.4 cpu fifo interface mode removed - no longer supported.
ds2232c version 1.4 ? future technology devices international ltd. 2005 page 51 of 54 FT2232C dual usb uart / fifo i.c. 11.0 disclaimer ? future technology devices international limited , 2002 - 2004 neither the whole nor any part of the information contained in, or the product described in this manual, may be adapted or reproduced in any material or electronic form without the prior written consent of the copyright holder . this product and its documentation are supplied on an as-is basis and no warranty as to their suitability for any particular purpose is either made or implied. future technology devices international ltd. will not accept any claim for damages howsoever arising as a result of use or failure of this product. your statutory rights are not affected. this product or any variant of it is not intended for use in any medical appliance, device or system in which the failure of the product might reasonably be expected to result in personal injury . this document provides preliminary information that may be subject to change without notice. 12.0 contact information future technology devices international. limited 373 scotland street, glasgow g5 8qb, united kingdom. tel : +44 ( 0 )141 429 2777 fax : +44 ( 0 )141 429 2758 e-mail ( sales ) : sales1@ftdichip.co m e-mail ( support ) : support1@ftdichip.co m e-mail ( general enquiries ) : admin1@ftdichip.co m web site url : http://www.ftdichip.co m agents and sales representatives at the time of writing our sales network covers over 40 different countries world-wide. please visit the sales network page of our web site for the contact details our distributor(s) in your country.

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